Special Reliability Features for Hf-Based High-k Gate Dielectrics

T. P. Ma, Fellow, IEEE, Huiming M. Bu, X. W. Wang, Liyang Y. Song, W. He, Miaomiao Wang, H.-H. Tseng,
and P. J. Tobin

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 5, NO. 1, MARCH 2005 (Invited Paper)

Purpose of the study:

HF-Based gate dielectrics are extensively investigated as alternatives to for future CMOS technology, but before any of these dielectrics can be selected by the semiconductor industry, its reliability must be satisfactorily demonstrated. This paper reviews some its recent reliability results.

Methods:

PolySi, TaSiN, or TiN gate MOSFETs were fabricated following a standard CMOS process on bulk silicon. ALD HfO2 of 4.4 nm in physical thickness deposited at 300 C with precursor, was used as the gate dielectric. Some of the MOSFETs had a silicon nitride cap layer of 0.5 nm thick between and gate for studying the effects of polySi/ reactions. The typical I–V and C–V characteristics for nMOSFETs are presented to show that the devices under study exhibit normal electrical characteristics. To measure the trapping-induced instability, constant voltage stress as well as pulse stress was applied to the polySi gate of MOSFETs in inversion. The threshold voltage shift, the midgap voltage shift and transconductance degradation caused by charge trapping were continuously monitored during the stress. Both pulsed voltage stress and dc constant voltage stress have been applied. Between each stressing period, there is a sensing period, in which the threshold voltage is measured.The threshold voltage shift is obtained from comparison with the initial one. Special attention is also paid to minimize the detrapping effect by using automatic program control to minimize the time interval between stressing and sensing. The density of the trapped charges, was derived from the midgap voltage shift. The interface trap density was obtained from ac conductance measurement. Voltage-dependent TDDB (time-dependent dielectric breakdown) measurements were used to determine the device lifetime. IETS spectra were taken on MOS capacitors by measuring the second harmonic signals with a standard lock-in method at liquid helium temperature (4.2 K). The modulation voltage of the excitation signal for the IETS measurements was 2 mV. A dual temperature (4.2 K, 77 K) technique was used to remove the elastic tunneling background.

Key findings:

1) The operating lifetime extracted from time-dependent-dielectric-breakdown (TDDB) is too optimistic, and the actual device lifetime is limited by the trapping-induced threshold voltage shift.

2) nMOSFETs are much more prone to trapping-induced than their pMOSFETs counterparts under normal operating conditions,due to much more electron traps than hole traps in HfO2-based gate dielectrics.

3) Metal gate yields improved reliability compared to polySi gate.